Many modern electronic systems employ a volatile memory for temporary storage, caching and buffering, such as a DRAM arranged as a plurality of memory dies organized into banks of devices which process commands. The dies are coupled to a memory controller by a bi-directional memory bus. The memory bus directs commands from a memory controller to the various dies, and directs data from the dies to the memory controller.
Termination resistors on the memory controller-side and on the die-side of the memory bus ensure signaling integrity on the memory bus line. The value of the termination resistors may be altered to change the I/O impedance to maintain signaling integrity over the bus despite changes in the temperature of the die.
In typical systems, the impedances at the I/O channel are recalibrated periodically after a set number of command cycles or a period of time, regardless of the temperature of the memory die and memory controller. This results in over-calibration of the I/O impedance in cases where the temperature of the memory die has not changed sufficiently to warrant a recalibration. Such unnecessary calibration of the I/O impedance uses power and occupies the bus such that no additional commands can be sent to memory dies during the recalibration, reducing the memory I/O performance.
Accordingly, there is a long-felt need to correct the problems inherent to present day systems.